1. Technical Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to testing techniques for integrated circuits.
2. Description of the Related Art
A technique known as Iddq testing is often used in defect testing of integrated circuits containing CMOS devices, for example. Iddq is the supply current conducted by a logic device when that device is in a quiescent state. Traditionally, detection of a high leakage current in an integrated circuit pointed to the presence of a defect and a current threshold was established to distinguish a xe2x80x9cgood devicexe2x80x9d from a xe2x80x9cbad devicexe2x80x9d. More specifically, conventional Iddq testing is performed by an ammeter used to measure the Iddq current of the device under test. However, such conventional testing has become impractical with the increased leakage currents effectuated by the reduction in geometries of each new generation of integrated circuits. Since the xe2x80x9cgood devicexe2x80x9d Iddq is increased, with reduced geometry ICs, a small amount of current conducted by a resistive short defect, for example, becomes a very small percentage of the overall current measured (i.e. reduced measurement resolution) making it difficult to effectively distinguish a xe2x80x9cgood devicexe2x80x9d from a xe2x80x9cbad devicexe2x80x9d. The additional current caused by the resistive short is most often smaller than the accuracy of conventional measurements and smaller than variations in xe2x80x9cgood devicexe2x80x9d Iddq from lot to lot.
In attempts to address this problem, most proposed solutions require special design for test (DFT) circuits to be added to the design of the device under test However, these DFT circuits add to the cost of the device while adding no value from the client perspective. For example, one DFT approach divides the power source connections of the device into multiple xe2x80x9cpower railsxe2x80x9d in place of the conventional single power rail. Because each power rail supplies a fraction of the total current of the device, the typical xe2x80x9cgood devicexe2x80x9d current for that power sector is smaller than the total for the full circuit. A resistive short can then be more easily detected because it will conduct a larger percentage of the measured current This approach has the disadvantages of requiring more device package pins for power supply connections and requiring extra design effort for power routing. Its purpose is also defeated in typical production testing environments because conventional ATE systems do not provide enough power sources to connect a separate source to each power rail of the device.
Another DFT approach divides the power connections of the device into a xe2x80x9ctree structuredxe2x80x9d power rail with each branch of the tree monitored by a Built-In Current Sensor (BICS). Each BICS is used to measure the current flow through its branch of the power rail. The BICS approach also relies on dividing the total current into smaller measured values so that resistive shorts can be more easily detected. It has the advantage, over the aforementioned DFT approach, that few package pins need be added to the device for test purposes. However, it also has the disadvantage that active test circuitry must be added to the design of the device under test as well as requiring extra design effort to form the tree structured power rails.
The present invention achieves technical advantages as a system and method for high resolution current measurements of integrated circuits. With the present invention, no DFT circuits are required. That is, no circuitry is added to the device design of a device under test to support the defect testing of the present system and method. Leakage current characterizing an integrated circuit is determined for at least one logic state of the integrated circuit from a sum of a first and second current measurement. A voltage source and a current source are used at different settings for each measurement and the measurements are summed for evaluation with an expected value.